| MATHEMATICS (TURKISH, PHD) | |||||
| PhD | TR-NQF-HE: Level 8 | QF-EHEA: Third Cycle | EQF-LLL: Level 8 | ||
| Course Code | Course Name | Semester | Theoretical | Practical | Credit | ECTS |
| CMP2007 | Digital System Design | Fall | 3 | 0 | 3 | 7 |
| The course opens with the approval of the Department at the beginning of each semester |
| Language of instruction: | En |
| Type of course: | Departmental Elective |
| Course Level: | |
| Mode of Delivery: | Face to face |
| Course Coordinator : | Dr. Öğr. Üyesi GÖRKEM KAR |
| Course Lecturer(s): |
Dr. Öğr. Üyesi SELÇUK BAKTIR Dr. UTKU GÜLEN Prof. Dr. TAŞKIN KOÇAK |
| Course Objectives: | This course covers digital logic design and system-level design using current state of the art in EDA tools. Students learn to design large-scale logic circuits from fundamental building blocks and methods. Topics include architectures of FPGAs, behavioral design specification, system partitioning, synthesis tools, design verification, and studies of novel systems implemented with FPGAs. Intended to familiarize students with the techniques and tools in ASIC designs. |
|
The students who have succeeded in this course; I. To understand fundamentals of boolean logic. II. To describe and design synchronous circuits. III. To describe and construct finite state machines. IV. To describe memory units and perform testing. V. To define the hardware architecture. VI. To perform hardware design language (HDL) |
| Logic design review. Behavioral Verilog coding. Design verification. Combinational and sequential circuit design using Verilog. Flip-flops, shift registers and counters. Algorithmic state machines. Designing large digital systems. Hierarchical description of circuits using structural Verilog coding. Memory and FPGA. |
| Week | Subject | Related Preparation | |
| 1) | Introduction to Digital System Design | ||
| 2) | Design metrics | ||
| 3) | Introduction to hardware description language (Verilog) | ||
| 4) | Introduction to Field Programmable Gate Array (FPGA) | ||
| 5) | Finite State Machines (FSM) | ||
| 6) | CMOS transistors | ||
| 7) | Timing part 2 | ||
| 8) | Review for the midterm exam | ||
| 9) | Timing part 2 | ||
| 10) | FSM - Sequence recognizer | ||
| 11) | Power and energy | ||
| 12) | Memory | ||
| 13) | Parallelism | ||
| 14) | Wrap-up and exam review | ||
| Course Notes: | Morris Mano, Michael Ciletti, Digital Design, Pearson, 4th Edition, 2008. Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, SunSoft Press, 1996. |
| References: |
| Semester Requirements | Number of Activities | Level of Contribution |
| Attendance | 14 | % 0 |
| Laboratory | 14 | % 20 |
| Application | 0 | % 0 |
| Field Work | 0 | % 0 |
| Special Course Internship (Work Placement) | 0 | % 0 |
| Quizzes | 10 | % 30 |
| Homework Assignments | 0 | % 0 |
| Presentation | 0 | % 0 |
| Project | 0 | % 0 |
| Seminar | 0 | % 0 |
| Midterms | 1 | % 10 |
| Preliminary Jury | % 0 | |
| Final | 1 | % 40 |
| Paper Submission | % 0 | |
| Jury | % 0 | |
| Bütünleme | % 0 | |
| Total | % 100 | |
| PERCENTAGE OF SEMESTER WORK | % 60 | |
| PERCENTAGE OF FINAL WORK | % 40 | |
| Total | % 100 | |
| Activities | Number of Activities | Duration (Hours) | Workload |
| Course Hours | 14 | 2 | 28 |
| Laboratory | 12 | 2 | 24 |
| Application | 0 | 0 | 0 |
| Special Course Internship (Work Placement) | 0 | 0 | 0 |
| Field Work | 0 | 0 | 0 |
| Study Hours Out of Class | 15 | 8 | 120 |
| Presentations / Seminar | 0 | 0 | 0 |
| Project | 0 | 0 | 0 |
| Homework Assignments | 0 | 0 | 0 |
| Quizzes | 10 | 1 | 10 |
| Preliminary Jury | 0 | 0 | 0 |
| Midterms | 1 | 2 | 2 |
| Paper Submission | 0 | 0 | 0 |
| Jury | 0 | 0 | 0 |
| Final | 1 | 2 | 2 |
| Total Workload | 186 | ||
| No Effect | 1 Lowest | 2 Low | 3 Average | 4 High | 5 Highest |
| Program Outcomes | Level of Contribution |