MATHEMATICS (TURKISH, PHD) | |||||
PhD | TR-NQF-HE: Level 8 | QF-EHEA: Third Cycle | EQF-LLL: Level 8 |
Course Code | Course Name | Semester | Theoretical | Practical | Credit | ECTS |
EEE5220 | Digital Design Automation | Fall | 3 | 0 | 3 | 12 |
The course opens with the approval of the Department at the beginning of each semester |
Language of instruction: | En |
Type of course: | Departmental Elective |
Course Level: | |
Mode of Delivery: | Face to face |
Course Coordinator : | Prof. Dr. ŞEREF KALEM |
Course Objectives: | System-on-a-Chip device integrates hundreds of millions of gates on a single die along with huge amount of code running simultaneously on microprocessors. Robustly implementing such complex systems within short window would be impossible without sophisticated and yet scalable computer-aided design (CAD) methods and tools that automatically generate low-level optimized hardware circuits and software binaries from higher level functional specifications. Course will begin with a general introduction to modern electronic system design flow and VLSI CAD. The course mainly focuses on high-level design techniques and automation algorithms for digital system design. |
The students who have succeeded in this course; Students will be able to: - Describe key concepts and approachs in high-level digital design automation. - Use C-based high-level synthesis tools to quickly design complex digital circuits. - Independently survey, present, and critique state-of-the-art research work in digital design automation. - Collaborate with others to develop new automation/optimization methods on new applications. |
Introduction, Algorithm review,C-based synthesis, Reconfigurable computing, Front-end compilation, Scheduling, Pipelining, Resource sharing, ASIPs, Dataflow models, Project meetings. |
Week | Subject | Related Preparation | |
1) | Introduction | ||
2) | Algorithm review | ||
3) | C-based synthesis | ||
4) | Reconfigurable computing | ||
5) | Front-end compilation | ||
6) | Paper discussions | ||
7) | Scheduling | ||
8) | Pipelining | ||
9) | Resource sharing | ||
10) | ASIPs | ||
11) | Midterm | ||
12) | Project discussions | ||
13) | Dataflow models | ||
14) | Project presentations |
Course Notes: | P. Schaumont, A Practical Introduction to Hardware/Software Codesign, Springer, 2010. |
References: | S. Dasgupta, C.H. Papadimitriou, and U.V. Vazirani, Algorithms, McGraw-Hill, 2007. |
Semester Requirements | Number of Activities | Level of Contribution |
Attendance | % 0 | |
Laboratory | % 0 | |
Application | % 0 | |
Field Work | % 0 | |
Special Course Internship (Work Placement) | % 0 | |
Quizzes | % 0 | |
Homework Assignments | % 0 | |
Presentation | % 0 | |
Project | 1 | % 30 |
Seminar | % 0 | |
Midterms | 1 | % 30 |
Preliminary Jury | % 0 | |
Final | 1 | % 40 |
Paper Submission | % 0 | |
Jury | % 0 | |
Bütünleme | % 0 | |
Total | % 100 | |
PERCENTAGE OF SEMESTER WORK | % 30 | |
PERCENTAGE OF FINAL WORK | % 70 | |
Total | % 100 |
Activities | Number of Activities | Duration (Hours) | Workload |
Course Hours | 14 | 3 | 42 |
Laboratory | 0 | 0 | 0 |
Application | 0 | 0 | 0 |
Special Course Internship (Work Placement) | 0 | 0 | 0 |
Field Work | 0 | 0 | 0 |
Study Hours Out of Class | 14 | 2 | 28 |
Presentations / Seminar | 0 | 0 | 0 |
Project | 1 | 20 | 20 |
Homework Assignments | 0 | 0 | 0 |
Quizzes | 0 | 0 | 0 |
Preliminary Jury | 0 | 0 | 0 |
Midterms | 1 | 30 | 30 |
Paper Submission | 0 | 0 | 0 |
Jury | 0 | 0 | 0 |
Final | 1 | 40 | 40 |
Total Workload | 160 |
No Effect | 1 Lowest | 2 Low | 3 Average | 4 High | 5 Highest |
Program Outcomes | Level of Contribution |