| MATHEMATICS (TURKISH, PHD) | |||||
| PhD | TR-NQF-HE: Level 8 | QF-EHEA: Third Cycle | EQF-LLL: Level 8 | ||
| Course Code | Course Name | Semester | Theoretical | Practical | Credit | ECTS |
| EEE4132 | Introduction to Integrated Circuit Design | Fall | 2 | 2 | 3 | 6 |
| The course opens with the approval of the Department at the beginning of each semester |
| Language of instruction: | En |
| Type of course: | Departmental Elective |
| Course Level: | |
| Mode of Delivery: | Face to face |
| Course Coordinator : | Prof. Dr. ŞEREF KALEM |
| Course Objectives: | Simple NMOS and CMOS logic gates. Processing and layout of bipolar and CMOS devices. Integrated circuit devices and modeling. NMOS and CMOS logic design. Transmission-gate and fully differential CMOS logic design. CMOS timing and I/O considerations. Latches, flip-flops, and synchronous system design. Bipolar and BiCMOS logic design. Static and dynamic random-access memory design. |
|
The students who have succeeded in this course; Upon successful completion of the course, students will be able to: 1. Analyze digital circuits. 2. Design digital circuits 3. Identify design stages of a digital circuit. 4. Relate given performance specifications to circuit design 5. Identify bottlenecks and limitations for a given design |
| 1 Introduction / Orientation 2 MOS transistor 3 Basic inverter. Design of buffer and I/O circuits 4 Basic inverter. Design of buffer and I/O circuits 5 Combinational logic 6 Combinational logic 7 Sequential logic 8 Midterm Exam 9 Sequential logic 10 Arithmetic building blocks: adders and multipliers 11 Arithmetic building blocks: adders and multipliers 12 Calculation of delay and power consumption, sizing of transistors. 13 Calculation of delay and power consumption, sizing of transistors. 14 Interconnect delay and impact on CMOS architectures 15 Interconnect delay and impact on CMOS architectures 16 Memory 17 Final Exam |
| Week | Subject | Related Preparation | |
| 1) | Introduction / Orientation | - | |
| 2) | MOS transistor | - | |
| 3) | Basic inverter. Design of buffer and I/O circuits | - | |
| 4) | Basic inverter. Design of buffer and I/O circuits | - | |
| 5) | Combinational logic | - | |
| 6) | Combinational logic | - | |
| 7) | Sequential logic | - | |
| 8) | Midterm Exam | - | |
| 9) | Sequential Sequential logiclogic | - | |
| 10) | Arithmetic building blocks: adders and multipliers | - | |
| 11) | Arithmetic building blocks: adders and multipliers | - | |
| 12) | Calculation of delay and power consumption, sizing of transistors | - | |
| 13) | Interconnect delay and impact on CMOS architectures | - | |
| 14) | Interconnect delay and impact on CMOS architectures | - | |
| 15) | Memory | - | |
| 16) | Final | - | |
| Course Notes: | Digital Integrated Circuits, 2/E Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, ISBN-10: 0130909963 ISBN-13: 9780130909961 Publisher: Prentice Hall Copyright: 2003 |
| References: | B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001. P. Gray, P. Hurst, S. Lewis,and R.G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th Edition, John Wiley and Sons, 2001 |
| Semester Requirements | Number of Activities | Level of Contribution |
| Attendance | 0 | % 0 |
| Laboratory | 0 | % 0 |
| Application | 0 | % 0 |
| Field Work | 0 | % 0 |
| Special Course Internship (Work Placement) | 0 | % 0 |
| Quizzes | 0 | % 0 |
| Homework Assignments | 0 | % 0 |
| Presentation | 0 | % 0 |
| Project | 0 | % 0 |
| Seminar | 0 | % 0 |
| Midterms | 1 | % 40 |
| Preliminary Jury | 0 | % 0 |
| Final | 1 | % 60 |
| Paper Submission | 0 | % 0 |
| Jury | 0 | % 0 |
| Bütünleme | % 0 | |
| Total | % 100 | |
| PERCENTAGE OF SEMESTER WORK | % 40 | |
| PERCENTAGE OF FINAL WORK | % 60 | |
| Total | % 100 | |
| Activities | Number of Activities | Duration (Hours) | Workload |
| Course Hours | 14 | 3 | 42 |
| Laboratory | 0 | 0 | 0 |
| Application | 0 | 0 | 0 |
| Special Course Internship (Work Placement) | 0 | 0 | 0 |
| Field Work | 0 | 0 | 0 |
| Study Hours Out of Class | 15 | 7 | 105 |
| Presentations / Seminar | 0 | 0 | 0 |
| Project | 0 | 0 | 0 |
| Homework Assignments | 0 | 0 | 0 |
| Quizzes | 0 | 0 | 0 |
| Preliminary Jury | 0 | ||
| Midterms | 1 | 3 | 3 |
| Paper Submission | 0 | ||
| Jury | 0 | ||
| Final | 1 | 2 | 2 |
| Total Workload | 152 | ||
| No Effect | 1 Lowest | 2 Low | 3 Average | 4 High | 5 Highest |
| Program Outcomes | Level of Contribution |