| MATHEMATICS (TURKISH, PHD) | |||||
| PhD | TR-NQF-HE: Level 8 | QF-EHEA: Third Cycle | EQF-LLL: Level 8 | ||
| Course Code | Course Name | Semester | Theoretical | Practical | Credit | ECTS |
| EEE4203 | Digital Integrated Circuit Design | Fall | 3 | 2 | 4 | 6 |
| The course opens with the approval of the Department at the beginning of each semester |
| Language of instruction: | En |
| Type of course: | Departmental Elective |
| Course Level: | |
| Mode of Delivery: | Face to face |
| Course Coordinator : | Prof. Dr. ŞEREF KALEM |
| Course Objectives: | This course will give you an overview of digital chip & FPGA design. It will emphasize literacy in chips as well as Verilog programming for digital design and verification. |
|
The students who have succeeded in this course; I. Describe what an what/why/how of ICs, FPGAs, and ASIC Flow. II. Apply verilog and basic digital design principles. III. Describe Scheduling, pipelining, resource sharing, hand shaking, UART, RS232 protocol. IV. Describe Memory inference, FIFO, Block RAMs, external RAMs. IP Core generator.VGA. V. Describe Analog-to-Digital Converters. VI. Explain the Pulse Width Modulator. Digital-to-Analog Converters. |
| 1.Week : The what/why/how of ICs, FPGAs, and ASIC Flow. MOS Transistors. CMOS Logic. CMOS Process. 2.Week : Verilog and basic digital design principles. Combinational logic. Data path. Adders, carry save trees, multipliers, priority encoders. Xilinx ISE. 3.Week : Verilog and basic digital design principles. Sequential Logic. Barrel shifter, counters. 4.Week : Design Verification Concepts. Simulation. Coverage. ModelSim. 5.Week : Scheduling. Pipelining. Resource sharing. Hand shaking. UART, RS232 protocol. 6.Week : PS/2 Mouse/Keyboard interface. 7.Week : Midterm1 8.Week : Memory inference, FIFO, Block RAMs, external RAMs. IP Core generator.VGA. 9.Week : Analog-to-Digital Converters. lab: Digital thermometer. 10.Week : Temperature sensing, measuring pressure, photosensing, motor control. 11.Week : Filters, OpAmp. 12.Week : Pulse Width Modulator. Digital-to-Analog Converters. 13.Week : Midterm 2 14.Week : Project Demos. |
| Week | Subject | Related Preparation | |
| 1) | The what/why/how of ICs, FPGAs, and ASIC Flow. MOS Transistors. CMOS Logic. CMOS Process. | - | |
| 2) | Verilog and basic digital design principles. Combinational logic. Data path. Adders, carry save trees, multipliers, priority encoders. Xilinx ISE. | - | |
| 3) | Verilog and basic digital design principles. Sequential Logic. Barrel shifter, counters. | - | |
| 4) | Design Verification Concepts. Simulation. Coverage. ModelSim. | - | |
| 5) | Scheduling. Pipelining. Resource sharing. Hand shaking. UART, RS232 protocol. | - | |
| 5) | PS/2 Mouse/Keyboard interface. | - | |
| 7) | Midterm 1 | - | |
| 8) | Memory inference, FIFO, Block RAMs, external RAMs. IP Core generator.VGA. | - | |
| 9) | Analog-to-Digital Converters. lab: Digital thermometer. | - | |
| 10) | Temperature sensing, measuring pressure, photosensing, motor control. | - | |
| 11) | Filters, OpAmp. | - | |
| 12) | Pulse Width Modulator. Digital-to-Analog Converters. | - | |
| 13) | Midterm 2 | - | |
| 14) | Project Demos. | - | |
| Course Notes: | 1. FPGA Prototyping By Verilog Examples by Pong P. Chu, Wiley |
| References: | 1. A Baker's Dozen Real Analog Solutions for Digital Designers by Bonnie Baker, Elsevier |
| Semester Requirements | Number of Activities | Level of Contribution |
| Attendance | % 0 | |
| Laboratory | % 0 | |
| Application | % 0 | |
| Field Work | % 0 | |
| Special Course Internship (Work Placement) | % 0 | |
| Quizzes | % 0 | |
| Homework Assignments | % 0 | |
| Presentation | % 0 | |
| Project | 2 | % 30 |
| Seminar | % 0 | |
| Midterms | 2 | % 30 |
| Preliminary Jury | % 0 | |
| Final | 2 | % 40 |
| Paper Submission | % 0 | |
| Jury | % 0 | |
| Bütünleme | % 0 | |
| Total | % 100 | |
| PERCENTAGE OF SEMESTER WORK | % 30 | |
| PERCENTAGE OF FINAL WORK | % 70 | |
| Total | % 100 | |
| Activities | Number of Activities | Duration (Hours) | Workload |
| Course Hours | 14 | 3 | 42 |
| Laboratory | 14 | 2 | 28 |
| Application | 0 | 0 | 0 |
| Special Course Internship (Work Placement) | 0 | 0 | 0 |
| Field Work | 0 | 0 | 0 |
| Study Hours Out of Class | 14 | 4 | 56 |
| Presentations / Seminar | 1 | 3 | 3 |
| Project | 1 | 10 | 10 |
| Homework Assignments | 0 | 0 | 0 |
| Quizzes | 0 | 0 | 0 |
| Preliminary Jury | 0 | 0 | 0 |
| Midterms | 2 | 3 | 6 |
| Paper Submission | 0 | 0 | 0 |
| Jury | 0 | 0 | 0 |
| Final | 1 | 2 | 2 |
| Total Workload | 147 | ||
| No Effect | 1 Lowest | 2 Low | 3 Average | 4 High | 5 Highest |
| Program Outcomes | Level of Contribution |